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Companion Guide

Implementation Guide

The practical "how-to" companion for your learning roadmap. Toolchain setup, code templates, troubleshooting, and career resources.

Free-Range VHDL Reference

Complete book chapters with code examples

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Quick Start

VHDL Environment

# Install GHDL (Linux/WSL)
sudo apt-get install ghdl gtkwave

# Install GHDL (macOS)
brew install ghdl

# Verify installation
ghdl --version

# Create project structure
mkdir -p vhdl_learning/{src,tb,sim}
cd vhdl_learning

Rust Environment

# Install Rust
curl --proto '=https' --tlsv1.2 -sSf \
  https://sh.rustup.rs | sh

# Add embedded targets
rustup target add thumbv7em-none-eabihf

# Install cargo tools
cargo install cargo-embed cargo-binutils

# Create automotive project
cargo new automotive_rust && cd automotive_rust

Essential Resources

VHDL

Rust

Automotive

  • ISOISO 11898 - CAN Bus Specification
  • ISOAUTOSAR Standards - Software architecture
  • SAESAE Papers - Industry standards
  • ISOISO 15765 - OBD-II Protocol

Troubleshooting

VHDL: Simulation-Synthesis Mismatch

Problem
process(clk)
begin
    if rising_edge(clk) then
        counter <= counter + 1;
        -- No reset! Works in sim,
        -- fails on hardware
    end if;
end process;
Solution
process(clk, reset)
begin
    if reset = '1' then
        counter <= (others => '0');
    elsif rising_edge(clk) then
        counter <= counter + 1;
    end if;
end process;

VHDL: Timing Violations

Problem
-- Long combinatorial path
Y <= A + B + C + D + E + F + G;
-- 7-level adder = slow
Solution: Pipeline
process(clk)
begin
    if rising_edge(clk) then
        stage1 <= A + B + C;
        stage2 <= D + E + F;
        stage3 <= stage1 + stage2 + G;
        Y <= stage3;
    end if;
end process;

VHDL: Unintended Latches

Problem
process(sel, A, B)
begin
    if sel = '1' then
        Y <= A;
    -- Missing else creates latch!
    end if;
end process;
Solution
process(sel, A, B)
begin
    if sel = '1' then
        Y <= A;
    else
        Y <= B;  -- Always assign!
    end if;
end process;

Rust-VHDL: Data Type Mismatch

Problem
// Rust: Little-endian
let data: [u8; 4] = [0x01, 0x02, 0x03, 0x04];

-- VHDL: Big-endian by default
-- data = x"01020304"
Solution
// Define byte order protocol
fn to_vhdl_bytes(data: u32) -> [u8; 4] {
    data.to_be_bytes()  // Big-endian
}

Hardware Recommendations

Beginner ($50-100)
  • FPGA: Lattice iCE40 UP5K board
  • MCU: STM32 Blue Pill + CAN transceiver
  • Sensors: BME280 (temp/pressure), MPU6050 (IMU)
Intermediate ($200-500)
  • FPGA: Xilinx Artix-7 (Basys 3 or Arty A7)
  • MCU: STM32 Nucleo with Ethernet
  • CAN: PEAK PCAN-USB adapter
Professional ($500+)
  • FPGA: Xilinx Zynq (ARM + FPGA)
  • CAN: Vector CANalyzer (industry standard)
  • Scope: Rigol DS1054Z (4-channel)

Career Integration

Target Roles

  • Embedded Systems Engineer - VHDL + Rust
  • Automotive Software Developer - CAN/OBD-II
  • FPGA Design Engineer - Digital systems
  • Firmware Engineer - Low-level programming
  • Controls Engineer - Real-time systems

Portfolio Projects

  • GitHub repos with clean documentation
  • Working hardware demos (video evidence)
  • Technical blog posts explaining designs
  • Contributions to open-source automotive tools
  • Personal vehicle CAN bus analysis project

You Are Ready When...

You can design a simple FSM without looking at examples
You instinctively add resets to all sequential logic
You understand why signals update at end of process
CAN message structure makes sense without references
You can read and write embedded Rust with no_std
Timing closure reports don't intimidate you